Electronic Design

ATE – Design for Test – Putting Memory to the Test in Nanometer Designs

Memory test at-speed isn't easy but can be achieved by balancing test selection, area overhead, and test-time constraints. The semiconductor industry has intensified its focus on yield issues to meet ...
Business Wire

Keithley Adds Support for Non-Volatile Memory, Very Low Frequency C-V, and Increased Parallel Testing to Semiconductor Parameter Analyzer

CLEVELAND--(BUSINESS WIRE)--Keithley Instruments, Inc., a world leader in advanced electrical test instruments and systems, has introduced a variety of enhancements for its award-winning Model ...
Electronic Design

The Challenges of Memory Mix Test

The variety of different test methodologies combined with today�s mixture of memory devices creates a complex test profile. The manufacturing test floor hums with activity; a range of memory devices ...
EDN

How to test high-speed memory with non-intrusive embedded instruments, Part 2

Having explained in part 1 the nature of the memory test challenge in the industry today, this article discusses non-intrusive debug and test methods based on embedded instruments and how these ...

New KV cache compaction technique cuts LLM memory 50x without accuracy loss

MIT researchers developed Attention Matching, a KV cache compaction technique that compresses LLM memory by 50x in seconds — ...
Yahoo Finance

TER's Memory Test Sales Hit $128M: Is the Growth Thesis Strengthening?

Teradyne TER is benefiting from the growing demand for memory test solutions, particularly driven by advancements in AI applications and data center investments. In the third quarter of 2025, the ...